1. Field of the Invention
The present invention relates to an enhanced reliability interrupt control apparatus in a data processing system.
2. Description of the Prior Art
Data processing systems basically include a central processor, a working memory and a plurality of peripheral units which are connected, either individually or in groups, to the central processor by means of suitable control interface units. The information transfer between central processor and peripheral units can take place according to several methods. But generally, when such transfer is required by the peripheral units, the method used most is the so-called "interrupt" method. According to the interrupt method, each peripheral unit which wants to exchange information with the central processor sends to the processor a signal indicative of an interrupt request. The central processor may then interrupt the execution of the program in progress and devote itself to servicing the interrupting peripheral unit. It is to be noted that several interrupts may be sent at the same time to the central processor by the several peripheral units. Obviously, the central processor can only service one interrupt at a time. It is therefore necessary to assign some priority criteria, that is to define which among several simultaneous interrupt requests has to be considered first. (It is to be noted that the interrupt requests are sent to the processor in a completely asynchronous way). It is therefore necessary that the central processor be provided with a synchronizing device which allows it to consider the highest priority interrupt during a fixed interval of time during its cycle. Among the several prior art solutions used to solve the above problems, the polling method or the cascade reciprocal conditioning method of the several interrupts are most often used, and require a latching register and an encoding network. Every peripheral unit is provided with a connection lead which transfers the interrupt request as a logical electrical signal at a predetermined level to a corresponding input terminal of the latching register. The latching register is cyclically enabled by a clock signal generated by the central processor and loads into its cells all the possible interrupt requests which are present when such clock signal occurs. The latching register output terminals are connected to a logic network which arranges, according to a predetermined priority, all the interrupt requests received on its input terminal and transfers to its output terminal only that interrupt request with the highest priority among all the possible interrupt requests present at the same time. The interrupt request thus transferred to the output terminal by the interrupt control apparatus is presented and used by the central processor in coded form. Obviously, the output terminal of the interrupt control apparatus has to be enabled with some delay after the time defined by the clock signal which latches the possible interrupts into the register. This is necessary in order to permit the signals to propagate inside the logic network as far as the output and have a stable state of the output signals.
Interrupt control apparatus of the type discussed are discribed in U.S. Pat. Nos. 3,534,339 and 4,001,784. However, such apparatus present problems. In the first place, the latching register must have a number of cells equal to the number of leads used for transferring separate interrupt signals, which are at least equal to the number of peripheral units. Additionally, if the peripheral units may send interrupt signals of different types on separate leads, the number of register cells has to be increased. It follows that, in the event of a great number of peripheral units, the latching register must have a large capacity and, therefore, is expensive. Although integrated circuits are available on the market which work as registers with a capacity of 4 or 8 bits, the 8-bit registers are not provided with a reset input which is essential during the initializing phase of the system. Accordingly, the designer must use a 4-bit register or, if 8-bit registers are chosen, additional logic elements must be used for an initializing reset circuit.
A further disadvantage of the prior art interrupt control apparatus is that noise pulses may be present on some interrupt leads during the time interval that the strobe signal latches the interrupt signals into the register. A noise pulse, if latched, is interpreted as an interrupt signal and may cause an erroneous working of the central processor.
These disadvantages are overcome by the interrupt control apparatus of the invention.